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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Mini-RISC-1                                                ////
////  Mini-Risc Core                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  D/L from: http://www.opencores.org/cores/minirisc/         ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
//
`timescale 1ns / 10ps
module mrisc(clk,
             rst_in,
             inst_addr,
             inst_data,
             portain,
             portbin,
             portcin,
             portaout,
             portbout,
             portcout,
             trisa,
             trisb,
             trisc,
             tcki,
             wdt_en);
  // Basic Core I/O.
  input clk;
  input rst_in;
  // Program memory interface
  output [10 : 0] inst_addr;
  input [11 : 0] inst_data;
  // Basic I/O Ports
  input [7 : 0] portain;
  input [7 : 0] portbin;
  input [7 : 0] portcin;
  output [7 : 0] portaout;
  output [7 : 0] portbout;
  output [7 : 0] portcout;
  output [7 : 0] trisa;
  output [7 : 0] trisb;
  output [7 : 0] trisc;
  input tcki;
  input wdt_en;
  // This should be set to the ROM location where our restart vector is.
  // As set here, we have 512 words of program space.
  parameter PC_RST_VECTOR = 11'h000, // Should be: 11'h7FF,
            STAT_RST_VALUE = 8'h18, OPT_RST_VALUE = 8'h3f, FSR_RST_VALUE = 7'h0, TRIS_RST_VALUE = 8'hff;
  parameter ALU_ADD = 4'h0, ALU_SUB = 4'h1, ALU_INC = 4'h2, ALU_DEC = 4'h3, ALU_AND = 4'h4, ALU_CLR = 4'h5, ALU_NOT = 4'h6, ALU_IOR = 4'h7, ALU_MOV = 4'h8, ALU_MOVW = 4'h9, ALU_RLF = 4'ha, ALU_RRF = 4'hb, ALU_SWP = 4'hc, ALU_XOR = 4'hd, ALU_BCF = 4'he, ALU_BSF = 4'hf;
  parameter // Byte Oriented RF Operations
  I_ADDWF = 12'b0001_11??_????, I_ANDWF = 12'b0001_01??_????, I_CLRF = 12'b0000_011?_????, I_CLRW = 12'b0000_0100_0000, I_COMF = 12'b0010_01??_????, I_DEC = 12'b0000_11??_????, I_DECFSZ = 12'b0010_11??_????, I_INCF = 12'b0010_10??_????, I_INCFSZ = 12'b0011_11??_????, I_IORWF = 12'b0001_00??_????, I_MOV = 12'b0010_00??_????, I_MOVWF = 12'b0000_001?_????, I_NOP = 12'b0000_0000_0000, I_RLF = 12'b0011_01??_????, I_RRF = 12'b0011_00??_????, I_SUBWF = 12'b0000_10??_????, I_SWAPF = 12'b0011_10??_????, I_XORWF = 12'b0001_10??_????,
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 // Bit Oriented RF Operations
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 I_BCF = 12'b0100_????_????, I_BSF = 12'b0101_????_????, I_BTFSC = 12'b0110_????_????, I_BTFSS = 12'b0111_????_????,
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    // Literal & Controll Operations
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    I_ANDLW = 12'b1110_????_????, I_CALL = 12'b1001_????_????, I_CLRWDT = 12'b0000_0000_0100, I_GOTO = 12'b101?_????_????, I_IORLW = 12'b1101_????_????, I_MOVLW = 12'b1100_????_????, I_OPTION = 12'b0000_0000_0010, I_RETLW = 12'b1000_????_????, I_SLEEP = 12'b0000_0000_0011, I_TRIS = 12'b0000_0000_0???, I_XORLW = 12'b1111_????_????;
  parameter // sfr register address encodings
  INDF_ADDR = 3'h0, TMR0_ADDR = 3'h1, PCL_ADDR = 3'h2, STAT_ADDR = 3'h3, FSR_ADDR = 3'h4, PORTA_ADDR = 3'h5, PORTB_ADDR = 3'h6, PORTC_ADDR = 3'h7;
  parameter // Source 1 Select
  K_SEL = 2'b10, SFR_SEL = 2'b00, RF_SEL = 2'b01;
  parameter // STATUS Register status bits we
  STAT_WR_C = 3'b001, STAT_WR_DC = 3'b010, STAT_WR_Z = 3'b100;
  // Instruction Register
  reg rst;
  reg [11 : 0] instr_0, instr_1;
  reg rst_r1, rst_r2;
  wire valid;
  reg valid_1;
  reg [7 : 0] mask;
  reg [7 : 0] sfr_rd_data;
  reg [3 : 0] alu_op;
  reg src1_sel;
  reg [1 : 0] src1_sel_;
  wire [7 : 0] dout; // ALU output
  wire [7 : 0] src1; // ALU Source 1
  reg [2 : 0] stat_bwe; // status bits we
  wire c_out, dc_out, z_out;
  reg pc_skz, pc_skz_;
  reg pc_bset, pc_bset_;
  reg pc_bclr, pc_bclr_;
  reg pc_call, pc_call_;
  reg pc_goto, pc_goto_;
  reg pc_retlw, pc_retlw_;
  wire invalidate_1;
  wire invalidate_0_;
  reg invalidate_0;
  // stage 1 dst decode
  reg w_we_;
  reg rf_we_;
  reg sfr_we_;
  reg tris_we_;
  // stage 2 dst decode
  reg w_we;
  wire rf_we;
  reg rf_we1, rf_we2, rf_we3;
  reg opt_we;
  reg trisa_we;
  reg trisb_we;
  reg trisc_we;
  wire indf_we_;
  reg tmr0_we;
  wire pc_we_;
  reg pc_we;
  reg stat_we;
  reg fsr_we;
  reg porta_we;
  reg portb_we;
  reg portc_we;
  wire bit_sel;
  wire [7 : 0] tmr0_next, tmr0_next1, tmr0_plus_1;
  wire tmr0_cnt_en;
  reg wdt_clr;
  wire wdt_to;
  wire wdt_en;
  wire tcki;
  wire [7 : 0] sfr_rd_data_tmp1, sfr_rd_data_tmp2, sfr_rd_data_tmp3;
  // Register File Connections
  wire [1 : 0] rf_rd_bnk, rf_wr_bnk;
  wire [4 : 0] rf_rd_addr, rf_wr_addr;
  wire [7 : 0] rf_rd_data, rf_wr_data;
  // Program Counter
  reg [10 : 0] inst_addr;
  reg [10 : 0] pc;
  wire [10 : 0] pc_next;
  wire [10 : 0] pc_plus_1;
  wire [10 : 0] stack_out;
  reg [10 : 0] pc_r, pc_r2;
  wire [10 : 0] pc_next1, pc_next2, pc_next3;
  // W Register
  reg [7 : 0] w; // Working Register
  reg [7 : 0] status; // Status Register
  wire [7 : 0] status_next;
  reg [6 : 0] fsr; // fsr register ( for indirect addressing)
  wire [6 : 0] fsr_next;
  reg [7 : 0] tmr0; // Timer 0
  reg [5 : 0] option; // Option Register
  // Tristate Control registers.
  reg [7 : 0] trisa;
  reg [7 : 0] trisb;
  reg [7 : 0] trisc;
  // I/O Port registers
  reg [7 : 0] porta_r; // PORTA input register
  reg [7 : 0] portb_r; // PORTB input register
  reg [7 : 0] portc_r; // PORTC input register
  reg [7 : 0] portaout; // PORTA output register
  reg [7 : 0] portbout; // PORTB output register
  reg [7 : 0] portcout; // PORTC output register
  ////////////////////////////////////////////////////////////////////////
  // External Reset is Synchrounous to clock
  always
    @(posedge clk)
      rst <= # 1 rst_in;
  ////////////////////////////////////////////////////////////////////////
  // Synchrounous Register File
  register_file u0(.clk(clk),
                   .rst(rst),
                   .rf_rd_bnk(rf_rd_bnk),
                   .rf_rd_addr(rf_rd_addr),
                   .rf_rd_data(rf_rd_data),
                   .rf_we(rf_we),
                   .rf_wr_bnk(rf_wr_bnk),
                   .rf_wr_addr(rf_wr_addr),
                   .rf_wr_data(rf_wr_data));
  ////////////////////////////////////////////////////////////////////////
  // Always Fetch Next Instruction
  always
    @(posedge clk)
      instr_0 <= # 1 inst_data;
  ////////////////////////////////////////////////////////////////////////
  // Instr Decode & Read Logic
  always
    @(posedge clk)
      begin
        rst_r1 <= # 1 rst | wdt_to;
        rst_r2 <= # 1 rst | rst_r1 | wdt_to;
      end
  assign valid = ~ rst_r2 & ~ invalidate_1;
  always
    @(posedge clk)
      valid_1 <= # 1 valid;
  always
    @(posedge clk)
      instr_1 <= # 1 instr_0;
  always
    @(posedge clk) // Basic Decode extracted directly from the instruction
      begin
        // Mask for bit modification instructions
        case (instr_0[7 : 5]) // synopsys full_case parallel_case
          0 :
            mask <= # 1 8'h01;
          1 :
            mask <= # 1 8'h02;
          2 :
            mask <= # 1 8'h04;
          3 :
            mask <= # 1 8'h08;
          4 :
            mask <= # 1 8'h10;
          5 :
            mask <= # 1 8'h20;
          6 :
            mask <= # 1 8'h40;
          7 :
            mask <= # 1 8'h80;
        endcase
      end
  always
    @(posedge clk)
      pc_r <= # 1 pc; // Previous version of PC to accomodate for pipeline
  always
    @(posedge clk) // SFR Read Operands
      if (src1_sel_[1])
        sfr_rd_data <= # 1 instr_0[7 : 0];
      else
        case (instr_0[2 : 0]) // synopsys full_case parallel_case
          1 :
            sfr_rd_data <= # 1 tmr0_next;
          2 :
            sfr_rd_data <= # 1 pc_r[7 : 0];
          3 :
            sfr_rd_data <= # 1 status_next;
          4 :
            sfr_rd_data <= # 1 { 1'b1, fsr_next };
          5 :
            sfr_rd_data <= # 1 porta_r;
          6 :
            sfr_rd_data <= # 1 portb_r;
          7 :
            sfr_rd_data <= # 1 portc_r;
        endcase
  /*
  always @(posedge clk)
          sfr_rd_data <= #1 sfr_rd_data_tmp1;


  reg     [3:0]   sfr_sel;
  wire    [3:0]   sfr_sel_src;

  assign  sfr_sel_src = {src1_sel_[1],instr_0[2:0]};

  always @(sfr_sel_src)
          casex(sfr_sel_src)      // synopsys full_case parallel_case
             4'b1_???:    sfr_sel = 4'b01_11;
             4'b0_001:    sfr_sel = 4'bxx_00;
             4'b0_010:    sfr_sel = 4'b00_11;
             4'b0_011:    sfr_sel = 4'bxx_01;
             4'b0_100:    sfr_sel = 4'bxx_10;
             4'b0_101:    sfr_sel = 4'b10_11;
             4'b0_11?:    sfr_sel = 4'b11_11;
          endcase


  mux4_8 u1(      .sel(sfr_sel[1:0]), .out(sfr_rd_data_tmp1),
                  .in0(tmr0_next), .in1(status_next),
                  .in2({1'b1, fsr_next}), .in3(sfr_rd_data_tmp2)  );

  mux4_8 u2(      .sel(sfr_sel[3:2]), .out(sfr_rd_data_tmp2),
                  .in0(pc_r[7:0]), .in1(instr_0[7:0]),
                  .in2(porta_r), .in3(sfr_rd_data_tmp3)   );

  mux2_8 u2b(     .sel(instr_0[0]), .out(sfr_rd_data_tmp3),
                  .in0(portb_r), .in1(portc_r)    );
  */
  reg instd_zero;
  always
    @(posedge clk)
      instd_zero <= # 1 ! (| inst_data[4 : 0]);
  // Register File Read Port
  assign rf_rd_bnk = fsr_next[6 : 5];
  assign rf_rd_addr = instd_zero ? fsr_next[4 : 0] : instr_0[4 : 0];
  // ALU OP
  always
    @(posedge clk)
      casex (instr_0) // synopsys full_case parallel_case
        // Byte Oriented RF Operations
        I_ADDWF :
          alu_op <= # 1 ALU_ADD; // ADDWF
        I_ANDWF :
          alu_op <= # 1 ALU_AND; // ANDWF
        I_CLRF :
          alu_op <= # 1 ALU_CLR; // CLRF
        I_CLRW :
          alu_op <= # 1 ALU_CLR; // CLRW
        I_COMF :
          alu_op <= # 1 ALU_NOT; // COMF
        I_DEC :
          alu_op <= # 1 ALU_DEC; // DEC
        I_DECFSZ :
          alu_op <= # 1 ALU_DEC; // DECFSZ
        I_INCF :
          alu_op <= # 1 ALU_INC; // INCF
        I_INCFSZ :
          alu_op <= # 1 ALU_INC; // INCFSZ
        I_IORWF :
          alu_op <= # 1 ALU_IOR; // IORWF
        I_MOV :
          alu_op <= # 1 ALU_MOV; // MOV
        I_MOVWF :
          alu_op <= # 1 ALU_MOVW; // MOVWF
        I_RLF :
          alu_op <= # 1 ALU_RLF; // RLF
        I_RRF :
          alu_op <= # 1 ALU_RRF; // RRF
        I_SUBWF :
          alu_op <= # 1 ALU_SUB; // SUBWF
        I_SWAPF :
          alu_op <= # 1 ALU_SWP; // SWAPF
        I_XORWF :
          alu_op <= # 1 ALU_XOR; // XORWF
        // Bit Oriented RF Operations
        I_BCF :
          alu_op <= # 1 ALU_BCF; // BCF
        I_BSF :
          alu_op <= # 1 ALU_BSF; // BSF
        // Literal & Controll Operations
        I_ANDLW :
          alu_op <= # 1 ALU_AND; // ANDLW
        I_IORLW :
          alu_op <= # 1 ALU_IOR; // IORLW
        I_MOVLW :
          alu_op <= # 1 ALU_MOV; // MOWLW
        I_RETLW :
          alu_op <= # 1 ALU_MOV; // RETLW
        I_XORLW :
          alu_op <= # 1 ALU_XOR; // XORLW
      endcase
  // Source Select
  // This CPU source 1 can be one of: rf (or sfr) or k,
  // second source (if any) is always w
  always
    @(instr_0)
      casex (instr_0) // synopsys full_case parallel_case
        I_ANDLW :
          src1_sel_ = K_SEL;
        I_CALL :
          src1_sel_ = K_SEL;
        I_GOTO :
          src1_sel_ = K_SEL;
        I_IORLW :
          src1_sel_ = K_SEL;
        I_MOVLW :
          src1_sel_ = K_SEL;
        I_RETLW :
          src1_sel_ = K_SEL;
        I_XORLW :
          src1_sel_ = K_SEL;
        default :
          src1_sel_ = ((instr_0[4 : 3] == 2'h0) & (instr_0[2 : 0] != 3'h0)) ? SFR_SEL : RF_SEL;
      endcase
  always
    @(posedge clk)
      src1_sel <= # 1 src1_sel_[0];
  // Destination Select
  // Destination can be one of: rf, w, option, tris OR one of sfr registers:
  // indf, tmr0, pc, status, fsr, porta, portb, portc, option, trisa, trisb, trisc
  // Stage 1
  // select w, pc, rf or sfr
  reg w_we1, w_we1_;
  always
    @(instr_0)
      begin
        casex (instr_0) // synopsys full_case parallel_case
          I_ADDWF, I_ANDWF, I_COMF, I_DEC, I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, I_MOV, I_RLF, I_RRF, I_SUBWF, I_SWAPF, I_XORWF : // w or f
            w_we1_ = 1;
          default :
            w_we1_ = 0;
        endcase
      end
  always
    @(instr_0)
      begin
        w_we_ = 0;
        rf_we_ = 0;
        sfr_we_ = 0;
        tris_we_ = 0;
        casex (instr_0) // synopsys full_case parallel_case
          I_ADDWF, I_ANDWF, I_COMF, I_DEC, I_DECFSZ, I_INCF, I_INCFSZ, I_IORWF, I_MOV, I_RLF, I_RRF, I_SUBWF, I_SWAPF, I_XORWF : // w or f
            begin
              rf_we_ = instr_0[5] & (instr_0[4] | instr_0[3]);
              sfr_we_ = instr_0[5] & ~ instr_0[4] & ~ instr_0[3];
            end
          I_MOVWF, I_CLRF, I_BCF, I_BSF : // only f
            begin
              rf_we_ = instr_0[4] | instr_0[3];
              sfr_we_ = ~ instr_0[4] & ~ instr_0[3];
            end
          I_CLRW, I_IORLW, I_MOVLW, I_ANDLW, I_RETLW, I_XORLW :
            w_we_ = 1; // only w
          I_TRIS :
            tris_we_ = 1; // trisa or trisb or trisc
        endcase
      end
  assign indf_we_ = sfr_we_ & (instr_0[2 : 0] == INDF_ADDR);
  assign pc_we_ = sfr_we_ & (instr_0[2 : 0] == PCL_ADDR);
  // Stage 2 destination encoder
  // write enable outputs are registered now
  always
    @(posedge clk)
      w_we <= # 1 w_we_; // working register write 0 enable
  always
    @(posedge clk)
      w_we1 <= # 1 w_we1_; // working register write 1 enable
  // Register File Write Enable is composed of thee conditions: 1) direct register writing (0x10-0x1f);
  // 2) Direct Global Register writing (0x08-0x0f), and 3) Indirect Register File Writing
  // The logic has been partitioned and balanced between the decode and execute stage ...
  assign rf_we = rf_we1 | (rf_we2 & rf_we3); // register file write enable Composite
  always
    @(posedge clk)
      rf_we1 <= # 1 valid & rf_we_; // register file write enable 1
  always
    @(posedge clk)
      rf_we2 <= # 1 valid & (fsr_next[4] | fsr_next[3]); // register file write enable 2
  always
    @(posedge clk)
      rf_we3 <= # 1 indf_we_; // register file write enable 3
  always
    @(posedge clk)
      wdt_clr <= # 1 instr_0[11 : 0] == I_CLRWDT;
  always
    @(posedge clk)
      opt_we <= # 1 instr_0[11 : 0] == I_OPTION;
  always
    @(posedge clk)
      trisa_we <= # 1 tris_we_ & (instr_0[2 : 0] == PORTA_ADDR);
  always
    @(posedge clk)
      trisb_we <= # 1 tris_we_ & (instr_0[2 : 0] == PORTB_ADDR);
  always
    @(posedge clk)
      trisc_we <= # 1 tris_we_ & (instr_0[2 : 0] == PORTC_ADDR);
  always
    @(posedge clk)
      begin
        // SFR registers
        tmr0_we <= # 1 sfr_we_ & (instr_0[2 : 0] == TMR0_ADDR);
        pc_we <= # 1 valid & pc_we_;
        stat_we <= # 1 valid & sfr_we_ & (instr_0[2 : 0] == STAT_ADDR);
        fsr_we <= # 1 valid & sfr_we_ & (instr_0[2 : 0] == FSR_ADDR);
        porta_we <= # 1 sfr_we_ & (instr_0[2 : 0] == PORTA_ADDR);
        portb_we <= # 1 sfr_we_ & (instr_0[2 : 0] == PORTB_ADDR);
        portc_we <= # 1 sfr_we_ & (instr_0[2 : 0] == PORTC_ADDR);
      end
  // Instructions that directly modify PC
  always
    @(instr_0)
      begin
        pc_skz_ = 0;
        pc_bset_ = 0;
        pc_bclr_ = 0;
        pc_call_ = 0;
        pc_goto_ = 0;
        pc_retlw_ = 0;
        casex (instr_0) // synopsys full_case parallel_case
          // Byte Oriented RF Operations
          I_DECFSZ, I_INCFSZ :
            pc_skz_ = 1;
          // Bit Oriented RF Operations
          I_BTFSS :
            pc_bset_ = 1;
          I_BTFSC :
            pc_bclr_ = 1;
          // Literal & Controll Operations
          I_CALL :
            pc_call_ = 1;
          I_GOTO :
            pc_goto_ = 1;
          I_RETLW :
            pc_retlw_ = 1;
        endcase
      end
  always
    @(posedge clk)
      begin
        pc_skz <= # 1 valid & pc_skz_;
        pc_bset <= # 1 valid & pc_bset_;
        pc_bclr <= # 1 valid & pc_bclr_;
        pc_call <= # 1 valid & pc_call_;
        pc_goto <= # 1 valid & pc_goto_;
        pc_retlw <= # 1 valid & pc_retlw_;
      end
  assign invalidate_0_ = (pc_call_ | pc_goto_ | pc_retlw_ | pc_we_);
  always
    @(posedge clk)
      invalidate_0 <= # 1 invalidate_0_;
  // Status bits WE
  always
    @(posedge clk)
      begin
        stat_bwe <= # 1 0;
        if (valid)
          casex (instr_0) // synopsys full_case parallel_case
            // Byte Oriented RF Operations
            I_ADDWF :
              stat_bwe <= # 1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z;
            I_ANDWF :
              stat_bwe <= # 1 STAT_WR_Z;
            I_CLRF :
              stat_bwe <= # 1 STAT_WR_Z;
            I_CLRW :
              stat_bwe <= # 1 STAT_WR_Z;
            I_COMF :
              stat_bwe <= # 1 STAT_WR_Z;
            I_DEC :
              stat_bwe <= # 1 STAT_WR_Z;
            I_INCF :
              stat_bwe <= # 1 STAT_WR_Z;
            I_IORWF :
              stat_bwe <= # 1 STAT_WR_Z;
            I_MOV :
              stat_bwe <= # 1 STAT_WR_Z;
            I_RLF :
              stat_bwe <= # 1 STAT_WR_C;
            I_RRF :
              stat_bwe <= # 1 STAT_WR_C;
            I_SUBWF :
              stat_bwe <= # 1 STAT_WR_C | STAT_WR_DC | STAT_WR_Z;
            I_XORWF :
              stat_bwe <= # 1 STAT_WR_Z;
            // Literal & Controll Operations
            I_ANDLW :
              stat_bwe <= # 1 STAT_WR_Z;
            //I_CLRWDT:                                  // Modifies TO & PD   *** FIX ME ***
            I_IORLW :
              stat_bwe <= # 1 STAT_WR_Z;
            //I_SLEEP:                                   // Modifies TO & PD   *** FIX ME ***
            I_XORLW :
              stat_bwe <= # 1 STAT_WR_Z;
          endcase
      end
  ////////////////////////////////////////////////////////////////////////
  // Wr & Execute Logic (including PC)
  // Second Pipeline Stage
  ////////////////////////////////////////////////////////////////////////
  // Source OP Sel
  //assign src1 = src1_sel ? rf_rd_data : sfr_rd_data;
  mux2_8 u3(.sel(src1_sel),
            .in0(sfr_rd_data),
            .in1(rf_rd_data),
            .out(src1));
  alu u4(.s1(src1),
         .s2(w),
         .mask(mask),
         .out(dout),
         .op(alu_op),
         .c_in(status[0]),
         .c(c_out),
         .dc(dc_out),
         .z(z_out));
  // Register file connections
  assign rf_wr_bnk = fsr[6 : 5];
  assign rf_wr_addr = (instr_1[4 : 0] == 0) ? fsr[4 : 0] : instr_1[4 : 0];
  assign rf_wr_data = dout;
  wire [7 : 0] status_next2;
  // Deal with all special registers (SFR) writes
  /*
  always @(rst or status or stat_we or stat_bwe or dout or c_out or dc_out or z_out)
          if(rst)         status_next = STAT_RST_VALUE;
          else
             begin
                  status_next = status;   // Default Keep Value
                  if(stat_we)     status_next = dout | 8'h18;
                  else
                     begin
                          if(stat_bwe[0]) status_next[0] = c_out;
                          if(stat_bwe[1]) status_next[1] = dc_out;
                          if(stat_bwe[2]) status_next[2] = z_out;
                     end
             end
  */
  assign status_next2[0] = stat_bwe[0] ? c_out : status[0];
  assign status_next2[1] = stat_bwe[1] ? dc_out : status[1];
  assign status_next2[2] = stat_bwe[2] ? z_out : status[2];
  mux2_8 u21(.sel(stat_we),
             .in1({ dout | 8'h18 }),
             .in0({ status[7 : 3], status_next2[2 : 0]}),
             .out(status_next));
  always
    @(posedge clk)
      if (rst)
        status <= # 1 STAT_RST_VALUE;
      else
        status <= # 1 status_next;
  //assign fsr_next = fsr_we ? dout[6:0] : fsr;
  mux2_7 u31(.sel(fsr_we),
             .in1(dout[6 : 0]),
             .in0(fsr),
             .out(fsr_next));
  always
    @(posedge clk)
      if (rst)
        fsr <= # 1 FSR_RST_VALUE;
      else
        fsr <= # 1 fsr_next;
  always
    @(posedge clk)
      if (valid_1 & (w_we | (w_we1 & ~ instr_1[5])))
        w <= # 1 dout;
  always
    @(posedge clk)
      if (rst)
        trisa <= # 1 TRIS_RST_VALUE;
      else
        if (trisa_we & valid_1)
          trisa <= # 1 w;
  always
    @(posedge clk)
      if (rst)
        trisb <= # 1 TRIS_RST_VALUE;
      else
        if (trisb_we & valid_1)
          trisb <= # 1 w;
  always
    @(posedge clk)
      if (rst)
        trisc <= # 1 TRIS_RST_VALUE;
      else
        if (trisc_we & valid_1)
          trisc <= # 1 w;
  always
    @(posedge clk)
      if (rst)
        option <= # 1 OPT_RST_VALUE;
      else
        if (opt_we & valid_1)
          option <= # 1 w[5 : 0];
  always
    @(posedge clk)
      if (porta_we & valid_1)
        portaout <= # 1 dout;
  always
    @(posedge clk)
      if (portb_we & valid_1)
        portbout <= # 1 dout;
  always
    @(posedge clk)
      if (portc_we & valid_1)
        portcout <= # 1 dout;
  always
    @(posedge clk)
      begin
        porta_r <= # 1 portain;
        portb_r <= # 1 portbin;
        portc_r <= # 1 portcin;
      end
  ///////////////////////////////////////////////////////////////////////
  // Timer Logic
  //assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? tmr0_plus_1 : tmr0;
  //assign tmr0_next = tmr0_we ? dout : tmr0_cnt_en ? (tmr0 + 1) : tmr0;
  mux2_8 u5(.sel(tmr0_we & valid_1),
            .in0(tmr0_next1),
            .in1(dout),
            .out(tmr0_next));
  mux2_8 u6(.sel(tmr0_cnt_en),
            .in0(tmr0),
            .in1(tmr0_plus_1),
            .out(tmr0_next1));
  inc8 u7(.in(tmr0),
          .out(tmr0_plus_1));
  always
    @(posedge clk)
      tmr0 <= # 1 tmr0_next;
  presclr_wdt u8(.clk(clk),
                 .rst(rst),
                 .tcki(tcki),
                 .option(option[5 : 0]),
                 .tmr0_we(tmr0_we & valid_1),
                 .tmr0_cnt_en(tmr0_cnt_en),
                 .wdt_en(wdt_en),
                 .wdt_clr(wdt_clr & valid_1),
                 .wdt_to(wdt_to));
  ////////////////////////////////////////////////////////////////////////
  // Programm Counter Logic
  always
    @(posedge clk)
      pc_r2 <= # 1 pc_r;
  // 'inst_addr' is a duplication of the 'pc'. The only time when it is really needed
  // is when the program memory is not on the chip and we want to place the registers
  // directly in the IO pads to reduce Tcq (For example in a Xilinx FPGA implementation).
  // If the program memory is on the chip or if the implmentation allows feedback from
  // registers in the IO cells, this is not needed. Synopsys FPGA compiler appears to
  // make the correct decission either way, and gett rid of unneded logic ...
  always
    @(posedge clk)
      if (rst)
        inst_addr <= # 1 PC_RST_VECTOR;
      else
        inst_addr <= # 1 pc_next;
  always
    @(posedge clk)
      if (rst)
        pc <= # 1 PC_RST_VECTOR;
      else
        pc <= # 1 pc_next;
  /*
  always @(pc_plus_1 or dout or pc_we or status or stack_out or
          pc_call or pc_goto or pc_retlw or instr_1)
          if(pc_we)       pc_next = {status[6:5], 1'b0, dout};
          else
          if(!pc_call & !pc_goto & !pc_retlw)     pc_next = pc_plus_1;
          else
          if(pc_call)     pc_next = {status[6:5], 1'b0, instr_1[7:0]};
          else
          if(pc_goto)     pc_next = {status[6:5], instr_1[8:0]};
          else
          if(pc_retlw)    pc_next = stack_out;
  */
  wire [10 : 0] pc_tmp1, pc_tmp2, pc_tmp3;
  wire pc_sel1;
  assign pc_tmp1 = { status[6 : 5], 1'b0, dout[7 : 0]};
  assign pc_tmp2 = { status[6 : 5], 1'b0, instr_1[7 : 0]};
  assign pc_tmp3 = { status[6 : 5], instr_1[8 : 0]};
  assign pc_sel1 = (! pc_call & ! pc_goto & ! pc_retlw);
  mux2_11 u9(.sel(pc_we),
             .in0(pc_next1),
             .in1(pc_tmp1),
             .out(pc_next));
  mux2_11 u10(.sel(pc_sel1),
              .in0(pc_next2),
              .in1(pc_plus_1),
              .out(pc_next1));
  mux2_11 u11(.sel(pc_call),
              .in0(pc_next3),
              .in1(pc_tmp2),
              .out(pc_next2));
  mux2_11 u12(.sel(pc_goto),
              .in0(stack_out),
              .in1(pc_tmp3),
              .out(pc_next3));
  inc11 u13(.in(pc),
            .out(pc_plus_1));
  reg invalidate_1_r1, invalidate_1_r2;
  assign invalidate_1 = (pc_skz & z_out) | (pc_bset & bit_sel) | (pc_bclr & ! bit_sel) | (invalidate_0 & valid_1) | invalidate_1_r1;
  always
    @(posedge clk)
      begin
        invalidate_1_r1 <= # 1 (invalidate_0 & valid_1) | invalidate_1_r2;
        invalidate_1_r2 <= # 1 (invalidate_0 & valid_1);
      end
  //assign bit_sel = src1[ instr_1[7:5] ];
  mux8_1 u22(.sel(instr_1[7 : 5]),
             .in(src1),
             .out(bit_sel));
  sfifo4x11 u14(.clk(clk),
                .push(pc_call),
                .din(pc_r2),
                .pop(pc_retlw),
                .dout(stack_out));
endmodule

Verilog Code after Obfuscation

Notice that comments are gone, names have been scrambled. The obfuscator uses a special list provided by the user to define names that should be preserved, ensuring that public interfaces and accesses to public libraries remain valid. If you obfuscate a set of Verilog source files simultaneously, only the public symbols they collectively offer will be sensibly named in the source files.


`timescale 1ns / 10ps
module O0(O1,
          O2,
          l3,
          O4,
          l5,
          O6,
          l7,
          O8,
          O9,
          la,
          lb,
          lc,
          ld,
          le,
          lf);
input O1;
input O2;
output [10 : 0] l3;
input [11 : 0] O4;
input [7 : 0] l5;
input [7 : 0] O6;
input [7 : 0] l7;
output [7 : 0] O8;
output [7 : 0] O9;
output [7 : 0] la;
output [7 : 0] lb;
output [7 : 0] lc;
output [7 : 0] ld;
input le;
input lf;
parameter lg = 11'h000, lh = 8'h18, li = 8'h3f, lj = 7'h0, Ok = 8'hff;
parameter Ol = 4'h0, Om = 4'h1, ln = 4'h2, Oo = 4'h3, lp = 4'h4, Oq = 4'h5, lr = 4'h6, Os = 4'h7, Ot = 4'h8, lu = 4'h9, Ov = 4'ha, Ow = 4'hb, lx = 4'hc, Oy = 4'hd, Oz = 4'he, O10 = 4'hf;
parameter l11 = 12'b0001_11??_????, l12 = 12'b0001_01??_????, O13 = 12'b0000_011?_????, l14 = 12'b0000_0100_0000, O15 = 12'b0010_01??_????, O16 = 12'b0000_11??_????, O17 = 12'b0010_11??_????, O18 = 12'b0010_10??_????, l19 = 12'b0011_11??_????, l1a = 12'b0001_00??_????, l1b = 12'b0010_00??_????, O1c = 12'b0000_001?_????, l1d = 12'b0000_0000_0000, O1e = 12'b0011_01??_????, l1f = 12'b0011_00??_????, l1g = 12'b0000_10??_????, O1h = 12'b0011_10??_????, l1i = 12'b0001_10??_????, l1j = 12'b0100_????_????, l1k = 12'b0101_????_????, O1l = 12'b0110_????_????, O1m = 12'b0111_????_????, O1n = 12'b1110_????_????, O1o = 12'b1001_????_????, O1p = 12'b0000_0000_0100, O1q = 12'b101?_????_????, l1r = 12'b1101_????_????, O1s = 12'b1100_????_????, l1t = 12'b0000_0000_0010, O1u = 12'b1000_????_????, l1v = 12'b0000_0000_0011, l1w = 12'b0000_0000_0???, O1x = 12'b1111_????_????;
parameter O1y = 3'h0, l1z = 3'h1, l20 = 3'h2, l21 = 3'h3, l22 = 3'h4, O23 = 3'h5, l24 = 3'h6, l25 = 3'h7;
parameter l26 = 2'b10, l27 = 2'b00, O28 = 2'b01;
parameter O29 = 3'b001, O2a = 3'b010, l2b = 3'b100;
reg l2c;
reg [11 : 0] O2d, l2e;
reg l2f, l2g;
wire O2h;
reg O2i;
reg [7 : 0] O2j;
reg [7 : 0] l2k;
reg [3 : 0] l2l;
reg O2m;
reg [1 : 0] l2n;
wire [7 : 0] l2o;
wire [7 : 0] l2p;
reg [2 : 0] l2q;
wire l2r, l2s, O2t;
reg l2u, O2v;
reg O2w, l2x;
reg l2y, O2z;
reg O30, O31;
reg O32, l33;
reg O34, l35;
wire l36;
wire O37;
reg O38;
reg O39;
reg l3a;
reg O3b;
reg l3c;
reg l3d;
wire O3e;
reg O3f, O3g, O3h;
reg l3i;
reg l3j;
reg O3k;
reg O3l;
wire O3m;
reg O3n;
wire l3o;
reg O3p;
reg O3q;
reg l3r;
reg l3s;
reg l3t;
reg O3u;
wire l3v;
wire [7 : 0] l3w, l3x, l3y;
wire O3z;
reg O40;
wire O41;
wire lf;
wire le;
wire [7 : 0] l42, O43, l44;
wire [1 : 0] l45, O46;
wire [4 : 0] l47, O48;
wire [7 : 0] l49, l4a;
reg [10 : 0] l3;
reg [10 : 0] O4b;
wire [10 : 0] l4c;
wire [10 : 0] O4d;
wire [10 : 0] l4e;
reg [10 : 0] O4f, l4g;
wire [10 : 0] O4h, l4i, l4j;
reg [7 : 0] l4k;
reg [7 : 0] O4l;
wire [7 : 0] O4m;
reg [6 : 0] l4n;
wire [6 : 0] l4o;
reg [7 : 0] O4p;
reg [5 : 0] l4q;
reg [7 : 0] lb;
reg [7 : 0] lc;
reg [7 : 0] ld;
reg [7 : 0] l4r;
reg [7 : 0] l4s;
reg [7 : 0] O4t;
reg [7 : 0] O8;
reg [7 : 0] O9;
reg [7 : 0] la;
always
@(posedge O1)
l2c <= # 1 O2;
l4u l4v(.O1(O1),
        .l2c(l2c),
        .l45(l45),
        .l47(l47),
        .l49(l49),
        .O3e(O3e),
        .O46(O46),
        .O48(O48),
        .l4a(l4a));
always
@(posedge O1)
O2d <= # 1 O4;
always
@(posedge O1)
begin
l2f <= # 1 l2c | O41;
l2g <= # 1 l2c | l2f | O41;
end
assign O2h = ~ l2g & ~ l36;
always
@(posedge O1)
O2i <= # 1 O2h;
always
@(posedge O1)
l2e <= # 1 O2d;
always
@(posedge O1)
begin
case (O2d[7 : 5])
0 :
O2j <= # 1 8'h01;
1 :
O2j <= # 1 8'h02;
2 :
O2j <= # 1 8'h04;
3 :
O2j <= # 1 8'h08;
4 :
O2j <= # 1 8'h10;
5 :
O2j <= # 1 8'h20;
6 :
O2j <= # 1 8'h40;
7 :
O2j <= # 1 8'h80;
endcase
end
always
@(posedge O1)
O4f <= # 1 O4b;
always
@(posedge O1)
if (l2n[1])
l2k <= # 1 O2d[7 : 0];
else
case (O2d[2 : 0])
1 :
l2k <= # 1 l3w;
2 :
l2k <= # 1 O4f[7 : 0];
3 :
l2k <= # 1 O4m;
4 :
l2k <= # 1 { 1'b1, l4o };
5 :
l2k <= # 1 l4r;
6 :
l2k <= # 1 l4s;
7 :
l2k <= # 1 O4t;
endcase
reg l4w;
always
@(posedge O1)
l4w <= # 1 ! (| O4[4 : 0]);
assign l45 = l4o[6 : 5];
assign l47 = l4w ? l4o[4 : 0] : O2d[4 : 0];
always
@(posedge O1)
casex (O2d)
l11 :
l2l <= # 1 Ol;
l12 :
l2l <= # 1 lp;
O13 :
l2l <= # 1 Oq;
l14 :
l2l <= # 1 Oq;
O15 :
l2l <= # 1 lr;
O16 :
l2l <= # 1 Oo;
O17 :
l2l <= # 1 Oo;
O18 :
l2l <= # 1 ln;
l19 :
l2l <= # 1 ln;
l1a :
l2l <= # 1 Os;
l1b :
l2l <= # 1 Ot;
O1c :
l2l <= # 1 lu;
O1e :
l2l <= # 1 Ov;
l1f :
l2l <= # 1 Ow;
l1g :
l2l <= # 1 Om;
O1h :
l2l <= # 1 lx;
l1i :
l2l <= # 1 Oy;
l1j :
l2l <= # 1 Oz;
l1k :
l2l <= # 1 O10;
O1n :
l2l <= # 1 lp;
l1r :
l2l <= # 1 Os;
O1s :
l2l <= # 1 Ot;
O1u :
l2l <= # 1 Ot;
O1x :
l2l <= # 1 Oy;
endcase
always
@(O2d)
casex (O2d)
O1n :
l2n = l26;
O1o :
l2n = l26;
O1q :
l2n = l26;
l1r :
l2n = l26;
O1s :
l2n = l26;
O1u :
l2n = l26;
O1x :
l2n = l26;
default :
l2n = ((O2d[4 : 3] == 2'h0) & (O2d[2 : 0] != 3'h0)) ? l27 : O28;
endcase
always
@(posedge O1)
O2m <= # 1 l2n[0];
reg O4x, l4y;
always
@(O2d)
begin
casex (O2d)
l11, l12, O15, O16, O17, O18, l19, l1a, l1b, O1e, l1f, l1g, O1h, l1i :
l4y = 1;
default :
l4y = 0;
endcase
end
always
@(O2d)
begin
O39 = 0;
l3a = 0;
O3b = 0;
l3c = 0;
casex (O2d)
l11, l12, O15, O16, O17, O18, l19, l1a, l1b, O1e, l1f, l1g, O1h, l1i :
begin
l3a = O2d[5] & (O2d[4] | O2d[3]);
O3b = O2d[5] & ~ O2d[4] & ~ O2d[3];
end
O1c, O13, l1j, l1k :
begin
l3a = O2d[4] | O2d[3];
O3b = ~ O2d[4] & ~ O2d[3];
end
l14, l1r, O1s, O1n, O1u, O1x :
O39 = 1;
l1w :
l3c = 1;
endcase
end
assign O3m = O3b & (O2d[2 : 0] == O1y);
assign l3o = O3b & (O2d[2 : 0] == l20);
always
@(posedge O1)
l3d <= # 1 O39;
always
@(posedge O1)
O4x <= # 1 l4y;
assign O3e = O3f | (O3g & O3h);
always
@(posedge O1)
O3f <= # 1 O2h & l3a;
always
@(posedge O1)
O3g <= # 1 O2h & (l4o[4] | l4o[3]);
always
@(posedge O1)
O3h <= # 1 O3m;
always
@(posedge O1)
O40 <= # 1 O2d[11 : 0] == O1p;
always
@(posedge O1)
l3i <= # 1 O2d[11 : 0] == l1t;
always
@(posedge O1)
l3j <= # 1 l3c & (O2d[2 : 0] == O23);
always
@(posedge O1)
O3k <= # 1 l3c & (O2d[2 : 0] == l24);
always
@(posedge O1)
O3l <= # 1 l3c & (O2d[2 : 0] == l25);
always
@(posedge O1)
begin
O3n <= # 1 O3b & (O2d[2 : 0] == l1z);
O3p <= # 1 O2h & l3o;
O3q <= # 1 O2h & O3b & (O2d[2 : 0] == l21);
l3r <= # 1 O2h & O3b & (O2d[2 : 0] == l22);
l3s <= # 1 O3b & (O2d[2 : 0] == O23);
l3t <= # 1 O3b & (O2d[2 : 0] == l24);
O3u <= # 1 O3b & (O2d[2 : 0] == l25);
end
always
@(O2d)
begin
O2v = 0;
l2x = 0;
O2z = 0;
O31 = 0;
l33 = 0;
l35 = 0;
casex (O2d)
O17, l19 :
O2v = 1;
O1m :
l2x = 1;
O1l :
O2z = 1;
O1o :
O31 = 1;
O1q :
l33 = 1;
O1u :
l35 = 1;
endcase
end
always
@(posedge O1)
begin
l2u <= # 1 O2h & O2v;
O2w <= # 1 O2h & l2x;
l2y <= # 1 O2h & O2z;
O30 <= # 1 O2h & O31;
O32 <= # 1 O2h & l33;
O34 <= # 1 O2h & l35;
end
assign O37 = (O31 | l33 | l35 | l3o);
always
@(posedge O1)
O38 <= # 1 O37;
always
@(posedge O1)
begin
l2q <= # 1 0;
if (O2h)
casex (O2d)
l11 :
l2q <= # 1 O29 | O2a | l2b;
l12 :
l2q <= # 1 l2b;
O13 :
l2q <= # 1 l2b;
l14 :
l2q <= # 1 l2b;
O15 :
l2q <= # 1 l2b;
O16 :
l2q <= # 1 l2b;
O18 :
l2q <= # 1 l2b;
l1a :
l2q <= # 1 l2b;
l1b :
l2q <= # 1 l2b;
O1e :
l2q <= # 1 O29;
l1f :
l2q <= # 1 O29;
l1g :
l2q <= # 1 O29 | O2a | l2b;
l1i :
l2q <= # 1 l2b;
O1n :
l2q <= # 1 l2b;
l1r :
l2q <= # 1 l2b;
O1x :
l2q <= # 1 l2b;
endcase
end
O4z O50(.O51(O2m),
        .l52(l2k),
        .l53(l49),
        .O54(l2p));
O55 O56(.l57(l2p),
        .O58(l4k),
        .O2j(O2j),
        .O54(l2o),
        .l59(l2l),
        .l5a(O4l[0]),
        .O5b(l2r),
        .O5c(l2s),
        .O5d(O2t));
assign O46 = l4n[6 : 5];
assign O48 = (l2e[4 : 0] == 0) ? l4n[4 : 0] : l2e[4 : 0];
assign l4a = l2o;
wire [7 : 0] O5e;
assign O5e[0] = l2q[0] ? l2r : O4l[0];
assign O5e[1] = l2q[1] ? l2s : O4l[1];
assign O5e[2] = l2q[2] ? O2t : O4l[2];
O4z O5f(.O51(O3q),
        .l53({ l2o | 8'h18 }),
        .l52({ O4l[7 : 3], O5e[2 : 0]}),
        .O54(O4m));
always
@(posedge O1)
if (l2c)
O4l <= # 1 lh;
else
O4l <= # 1 O4m;
O5g l5h(.O51(l3r),
        .l53(l2o[6 : 0]),
        .l52(l4n),
        .O54(l4o));
always
@(posedge O1)
if (l2c)
l4n <= # 1 lj;
else
l4n <= # 1 l4o;
always
@(posedge O1)
if (O2i & (l3d | (O4x & ~ l2e[5])))
l4k <= # 1 l2o;
always
@(posedge O1)
if (l2c)
lb <= # 1 Ok;
else
if (l3j & O2i)
lb <= # 1 l4k;
always
@(posedge O1)
if (l2c)
lc <= # 1 Ok;
else
if (O3k & O2i)
lc <= # 1 l4k;
always
@(posedge O1)
if (l2c)
ld <= # 1 Ok;
else
if (O3l & O2i)
ld <= # 1 l4k;
always
@(posedge O1)
if (l2c)
l4q <= # 1 li;
else
if (l3i & O2i)
l4q <= # 1 l4k[5 : 0];
always
@(posedge O1)
if (l3s & O2i)
O8 <= # 1 l2o;
always
@(posedge O1)
if (l3t & O2i)
O9 <= # 1 l2o;
always
@(posedge O1)
if (O3u & O2i)
la <= # 1 l2o;
always
@(posedge O1)
begin
l4r <= # 1 l5;
l4s <= # 1 O6;
O4t <= # 1 l7;
end
O4z l5i(.O51(O3n & O2i),
        .l52(l3x),
        .l53(l2o),
        .O54(l3w));
O4z l5j(.O51(O3z),
        .l52(O4p),
        .l53(l3y),
        .O54(l3x));
l5k O5l(.O5m(O4p),
        .O54(l3y));
always
@(posedge O1)
O4p <= # 1 l3w;
l5n O5o(.O1(O1),
        .l2c(l2c),
        .le(le),
        .l4q(l4q[5 : 0]),
        .O3n(O3n & O2i),
        .O3z(O3z),
        .lf(lf),
        .O40(O40 & O2i),
        .O41(O41));
always
@(posedge O1)
l4g <= # 1 O4f;
always
@(posedge O1)
if (l2c)
l3 <= # 1 lg;
else
l3 <= # 1 l4c;
always
@(posedge O1)
if (l2c)
O4b <= # 1 lg;
else
O4b <= # 1 l4c;
wire [10 : 0] O5p, O5q, O5r;
wire O5s;
assign O5p = { O4l[6 : 5], 1'b0, l2o[7 : 0]};
assign O5q = { O4l[6 : 5], 1'b0, l2e[7 : 0]};
assign O5r = { O4l[6 : 5], l2e[8 : 0]};
assign O5s = (! O30 & ! O32 & ! O34);
O5t l5u(.O51(O3p),
        .l52(O4h),
        .l53(O5p),
        .O54(l4c));
O5t l5v(.O51(O5s),
        .l52(l4i),
        .l53(O4d),
        .O54(O4h));
O5t O5w(.O51(O30),
        .l52(l4j),
        .l53(O5q),
        .O54(l4i));
O5t l5x(.O51(O32),
        .l52(l4e),
        .l53(O5r),
        .O54(l4j));
O5y O5z(.O5m(O4b),
        .O54(O4d));
reg l60, O61;
assign l36 = (l2u & O2t) | (O2w & l3v) | (l2y & ! l3v) | (O38 & O2i) | l60;
always
@(posedge O1)
begin
l60 <= # 1 (O38 & O2i) | O61;
O61 <= # 1 (O38 & O2i);
end
l62 l63(.O51(l2e[7 : 5]),
        .O5m(l2p),
        .O54(l3v));
l64 l65(.O1(O1),
        .l66(O30),
        .l67(l4g),
        .l68(O34),
        .l2o(l4e));
endmodule

Obfuscated Symbol Cross Reference

The obfuscator produces a cross reference mapping obfuscated symbols to the orginal symbols, so that obfuscated code in the field can still be decoded if necessary. In fact, by reversing this map, the obfuscator can unobfuscate the code (of course, it cannot restore the comments).


ALU_ADD -> Ol
ALU_AND -> lp
ALU_BCF -> Oz
ALU_BSF -> O10
ALU_CLR -> Oq
ALU_DEC -> Oo
ALU_INC -> ln
ALU_IOR -> Os
ALU_MOV -> Ot
ALU_MOVW -> lu
ALU_NOT -> lr
ALU_RLF -> Ov
ALU_RRF -> Ow
ALU_SUB -> Om
ALU_SWP -> lx
ALU_XOR -> Oy
FSR_ADDR -> l22
FSR_RST_VALUE -> lj
INDF_ADDR -> O1y
I_ADDWF -> l11
I_ANDLW -> O1n
I_ANDWF -> l12
I_BCF -> l1j
I_BSF -> l1k
I_BTFSC -> O1l
I_BTFSS -> O1m
I_CALL -> O1o
I_CLRF -> O13
I_CLRW -> l14
I_CLRWDT -> O1p
I_COMF -> O15
I_DEC -> O16
I_DECFSZ -> O17
I_GOTO -> O1q
I_INCF -> O18
I_INCFSZ -> l19
I_IORLW -> l1r
I_IORWF -> l1a
I_MOV -> l1b
I_MOVLW -> O1s
I_MOVWF -> O1c
I_NOP -> l1d
I_OPTION -> l1t
I_RETLW -> O1u
I_RLF -> O1e
I_RRF -> l1f
I_SLEEP -> l1v
I_SUBWF -> l1g
I_SWAPF -> O1h
I_TRIS -> l1w
I_XORLW -> O1x
I_XORWF -> l1i
K_SEL -> l26
OPT_RST_VALUE -> li
PCL_ADDR -> l20
PC_RST_VECTOR -> lg
PORTA_ADDR -> O23
PORTB_ADDR -> l24
PORTC_ADDR -> l25
RF_SEL -> O28
SFR_SEL -> l27
STAT_ADDR -> l21
STAT_RST_VALUE -> lh
STAT_WR_C -> O29
STAT_WR_DC -> O2a
STAT_WR_Z -> l2b
TMR0_ADDR -> l1z
TRIS_RST_VALUE -> Ok
alu -> O55
alu_op -> l2l
bit_sel -> l3v
c -> O5b
c_in -> l5a
c_out -> l2r
clk -> O1
dc -> O5c
dc_out -> l2s
din -> l67
dout -> l2o
fsr -> l4n
fsr_next -> l4o
fsr_we -> l3r
in -> O5m
in0 -> l52
in1 -> l53
inc11 -> O5y
inc8 -> l5k
indf_we_ -> O3m
inst_addr -> l3
inst_data -> O4
instd_zero -> l4w
instr_0 -> O2d
instr_1 -> l2e
invalidate_0 -> O38
invalidate_0_ -> O37
invalidate_1 -> l36
invalidate_1_r1 -> l60
invalidate_1_r2 -> O61
mask -> O2j
mrisc -> O0
mux2_11 -> O5t
mux2_7 -> O5g
mux2_8 -> O4z
mux8_1 -> l62
op -> l59
opt_we -> l3i
option -> l4q
out -> O54
pc -> O4b
pc_bclr -> l2y
pc_bclr_ -> O2z
pc_bset -> O2w
pc_bset_ -> l2x
pc_call -> O30
pc_call_ -> O31
pc_goto -> O32
pc_goto_ -> l33
pc_next -> l4c
pc_next1 -> O4h
pc_next2 -> l4i
pc_next3 -> l4j
pc_plus_1 -> O4d
pc_r -> O4f
pc_r2 -> l4g
pc_retlw -> O34
pc_retlw_ -> l35
pc_sel1 -> O5s
pc_skz -> l2u
pc_skz_ -> O2v
pc_tmp1 -> O5p
pc_tmp2 -> O5q
pc_tmp3 -> O5r
pc_we -> O3p
pc_we_ -> l3o
pop -> l68
porta_r -> l4r
porta_we -> l3s
portain -> l5
portaout -> O8
portb_r -> l4s
portb_we -> l3t
portbin -> O6
portbout -> O9
portc_r -> O4t
portc_we -> O3u
portcin -> l7
portcout -> la
presclr_wdt -> l5n
push -> l66
register_file -> l4u
rf_rd_addr -> l47
rf_rd_bnk -> l45
rf_rd_data -> l49
rf_we -> O3e
rf_we1 -> O3f
rf_we2 -> O3g
rf_we3 -> O3h
rf_we_ -> l3a
rf_wr_addr -> O48
rf_wr_bnk -> O46
rf_wr_data -> l4a
rst -> l2c
rst_in -> O2
rst_r1 -> l2f
rst_r2 -> l2g
s1 -> l57
s2 -> O58
sel -> O51
sfifo4x11 -> l64
sfr_rd_data -> l2k
sfr_rd_data_tmp1 -> l42
sfr_rd_data_tmp2 -> O43
sfr_rd_data_tmp3 -> l44
sfr_we_ -> O3b
src1 -> l2p
src1_sel -> O2m
src1_sel_ -> l2n
stack_out -> l4e
stat_bwe -> l2q
stat_we -> O3q
status -> O4l
status_next -> O4m
status_next2 -> O5e
tcki -> le
tmr0 -> O4p
tmr0_cnt_en -> O3z
tmr0_next -> l3w
tmr0_next1 -> l3x
tmr0_plus_1 -> l3y
tmr0_we -> O3n
tris_we_ -> l3c
trisa -> lb
trisa_we -> l3j
trisb -> lc
trisb_we -> O3k
trisc -> ld
trisc_we -> O3l
u0 -> l4v
u10 -> l5v
u11 -> O5w
u12 -> l5x
u13 -> O5z
u14 -> l65
u21 -> O5f
u22 -> l63
u3 -> O50
u31 -> l5h
u4 -> O56
u5 -> l5i
u6 -> l5j
u7 -> O5l
u8 -> O5o
u9 -> l5u
valid -> O2h
valid_1 -> O2i
w -> l4k
w_we -> l3d
w_we1 -> O4x
w_we1_ -> l4y
w_we_ -> O39
wdt_clr -> O40
wdt_en -> lf
wdt_to -> O41
z -> O5d
z_out -> O2t
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Verilog
Obfuscator Example