Verilog Source Code Obfuscator

The Verilog Obfuscator tool scrambles Verilog source code to make it very difficult to understand or reverse-engineer (example). This provides significant protection for source code intellectual property that must be shipped to a customer. It is a member of SD's family of Source Code Obfuscators.

Verilog Obfuscator Features

  • Verisions to Handle Verilog 1995, 2001, 2012, and SystemVerilog3p1a
  • Replaces names by nonsense names without affecting functionality
    • User definable list of preserved names
  • Strips comments and removes most source code structure
    • User definable comment filtering, to preserve Copyright and Synthesis directives
  • No changes to the customer Verilog compilation or execution procedures or environment
  • Option to neatly format Verilog source code as aid to developer before obfuscation
  • Output encoding in ASCII, European ASCII, or UNICODE
  • Command line and GUI interfaces
  • Supports Xilinx tools requirements for uppercase symbols

Download an evaluation version

Semantic Designs also offers a VHDL obfuscator, a SystemVerilog obfuscator, and a SystemC obfuscator.

For more information:    Follow us at Twitter: @SemanticDesigns